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Area-efficent power clamp circuit using gatecoupled structure for smart power ICs
- Kim, Dong-Jun;
- Park, Ju-Ho;
- Park, Sang Gyu
Citations
SCOPUS
3초록
Area-efficient ESD (Electro Static Discharge) power clamp using gate-coupled structure for Smart Power technology is proposed. The use of Big-FET parasitic Capacitance results in the reduction of the total size of the circuit when compared to the Darlington scheme and RC triggered circuits. The performance of the proposed ESD power clamp was successfully verified in a 0.35um 60V BCD (Bipolar CMOS DMOS) process by TLP (Transmission Line Pulse) measurements.
키워드
Component; Electrostatic discharge (ESD); Gatecoupled structure; Power clamp circui; Smart power technology; Component; Electrostatic discharge (ESD); Gatecoupled structure; Power clamp circui; Smart power technology; Clamping devices; Electrostatic discharge; Programmable logic controllers; Electrostatic devices
- 제목
- Area-efficent power clamp circuit using gatecoupled structure for smart power ICs
- 저자
- Kim, Dong-Jun; Park, Ju-Ho; Park, Sang Gyu
- 발행일
- 2008-11
- 유형
- Conference Paper
- 저널명
- 2008 International SoC Design Conference, ISOCC 2008
- 권
- 1
- 페이지
- I429 ~ I430
- 언어
- ENG
- 출판사
- IEEE
- 발행국가
- 미국
- ISSN
- P 0000-0000