A 108-Gb/s PAM-8 CTLE + FFE Receiver Front-End With 1.4-Vppd Input Range in 28-nm CMOS

초록

This article presents a 108-Gb/s 8-level pulse amplitude modulation (PAM-8) receiver front-end capable of handling a wide input dynamic range to overcome the signal-to-noise ratio (SNR) versus linearity tradeoff in higher-order modulation schemes. The proposed architecture employs a multi-path continuous-time linear equalizer (CTLE) with a bias-shifting technique, which splits the input dynamic range to maintain high linearity even with a large input swing of 1.4 Vppd. To further enhance signal integrity without introducing non-linear distortion, a single-path shared feed-forward equalizer (FFE) is used. This FFE signaling path utilizes passive attenuators and track-and-hold (TAH) circuits driven by a custom 75% duty-cycle clock generator to ensure sufficient timing margins for analog tap delays. Additionally, a background statistical calibration algorithm based on output probability is implemented to automatically optimize the offset voltages for the sub-ranging configuration. The prototype was fabricated in 28-nm CMOS technology, occupying an active area of 0.255 mm2. Measurement results demonstrate that the receiver successfully processes 108-Gb/s PAM-8 signals over a channel with 10.7-dB loss at 18 GHz, achieving an energy efficiency of 1.95 pJ/bit.

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