BRAM-Free ML-KEM NTT with SRL-Based Reordering Unit

초록

The module-lattice-based key encapsulation mechanism (ML-KEM), standardized by the National Institute of Standards and Technology (NIST), is a key encapsulation scheme based on module learning with errors (MLWE). Its core computation relies on polynomial multiplication using the number theoretic transform (NTT), which is executed as a sequence of NTT–point-wise multiplication (PWM)–inverse NTT (INTT). This work presents a BRAM-free NTT architecture employing a shift-register lookup table (SRL)-based Reordering Unit (RU) to eliminate memory access and address-generation overheads. The RU consists of seven SRL-based clusters that enable conflict-free data reordering across stages, while the Butterfly Unit (BU) adopts a BRAM-free datapath to remove on-chip memory latency along the BU–RU–BU critical path. The proposed design was implemented on a Xilinx Artix-7 (AC701) platform, achieving 294 MHz operating frequency using 1132 LUTs, 561 FFs, 346 slices, 0 BRAMs, and 2 DSPs. For NTT/INTT/PWM operations, the design requires 458/458/275 cycles, and demonstrates 11–89% improvement in area-time product (ATP) compared with representative Artix-7 designs. The proposed SRL-based, BRAM-free datapath effectively eliminates data conflicts and provides a compact and high-throughput hardware solution for ML-KEM.

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