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An efficient check node operation circuit for Min-Sum based LDPC decoder
- Cho, Keol;
- Chung, Ki-Seok
Citations
SCOPUS
0초록
This paper presents a low power and area-efficient check node operation circuit for LDPC decoders based on Min-Sum algorithm. By improving a heavily used comparator circuit, our proposed check node unit reduces area and power consumption by 8% and 13%, respectively, without decoding speed degradation compared to conventional LDPC decoders.
키워드
circuit size; LDPC decoder; low power; low-density parity-check codes; Algorithms; Consumer electronics; Decoding; Area-Efficient; Check node units; Circuit size; Decoding speed; LDPC decoder; Low Power; Low-density parity-check (LDPC) codes; Min-Sum algorithm; Low power electronics
- 제목
- An efficient check node operation circuit for Min-Sum based LDPC decoder
- 저자
- Cho, Keol; Chung, Ki-Seok
- 발행일
- 2014-04
- 유형
- Conference Paper
- 저널명
- Proceedings of the International Symposium on Consumer Electronics, ISCE
- 페이지
- 1 ~ 2