Reduce Cell to Cell Charge Interference by Virtual Ground Inclusion in 3-Dimensional Vertical Gate NAND Flash Memory

초록

In this work, we propose a structural modification to the 3-dimensional vertical gate NAND flash memory that will reduce the charge interference caused by stored charge on the opposite facing cell. In the barrier oxide structure (BOS), an oxide layer was inserted into the center of the body to physically block the conduction electrons moving to and from the channel regions influenced by the charge stored on either of the Oxide-Nitride-Oxide (ONO) trap layers. In the virtual ground structure (VGS), a highly p-type doped poly silicon layer was inserted to act as a virtual ground to reduce the electric-field changes caused by the stored change on the ONO trap layers. We investigated the I-V characteristics of the different structures using 3-D TOAD simulation tool, depending on the body type (crystalline or poly silicon) at double programming and single programming. We confirmed that the charge interference problem was reduced significantly by the BOS and VGS modifications in the crystalline silicon and high quality poly silicon body structures.

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