Lowering Error Floors of Systematic LDPC Codes Using Data Shortening

초록

In this paper, data shortening methods for lowering error floors of systematic LDPC codes are proposed. Rather than attempting to analyze trapping (or stopping) sets of a given LDPC code rigorously, we search information bits associated with dominant trapping (or stopping) sets of systematic LDPC codes through simulation under various channels. Then, proper information bits forming dominant trapping (or stopping) sets are selected and known values are assigned to them before encoding to weaken the effect of dominant trapping (or stopping) sets. To decode codewords, fixed known values are assigned to the selected information bits, which gives rise to the disconnection of some edges in dominant trapping (or stopping) sets. Through simulation, it is shown that the proposed schemes result in remarkably better performance, especially at the error floor region, than the base LDPC codes under various channels with negligible loss of code rate.

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