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A 12-Gb/s Baud-rate Clock and Data Recovery with 75% Phase-detection Probability by Precoding and Integration-Hold-Reset Frontend
- Seo, Hyeongmin;
- Han, Jiyun;
- Kim, Kyungmin;
- Lim, Baekjin;
- Shin, Eunseok;
- ... Han, Jaeduk;
- 외 5명
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2초록
This paper describes a 12-Gb/s quarter-rate receiver with a current-integrating baud-rate clock and data recovery (CDR) technique. The proposed CDR receives a pre-encoded non-return-to-zero (NRZ) data stream and integrates with 0.5-UI phase offset to extract the phase information. By sampling three consecutive symbols with multiple thresholds in the proposed phase detector, the CDR achieves a 75% phase-detection probability, which is the highest among baud-rate CDRs and leads to a better tracking bandwidth and jitter tolerance. The 12-Gb/s baud-rate CDR prototype is implemented in a 28 nm CMOS process and consumes 77 mW from a 1.2-V supply.
키워드
Clocks; Symbols; Receivers; Timing; Phase detection; Jitter; Precoding; Baud-rate CDR; current integration; transition probability; receiver; DFE; CDR
- 제목
- A 12-Gb/s Baud-rate Clock and Data Recovery with 75% Phase-detection Probability by Precoding and Integration-Hold-Reset Frontend
- 저자
- Seo, Hyeongmin; Han, Jiyun; Kim, Kyungmin; Lim, Baekjin; Shin, Eunseok; Choi, Youngdon; Ko, Hyungjong; Choi, Jung-Hwan; Lee, Sang-Hyun; Yoo, Changsik; Han, Jaeduk
- 발행일
- 2023-02
- 유형
- Article
- 권
- 70
- 호
- 2
- 페이지
- 411 ~ 415