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Reduced distribution of threshold voltage shift in double layer NiSi 2 nanocrystals for nano-floating gate memory applications
- Choi, Sung-Jin;
- Lee, Jun-Hyuk;
- Kim, Dong-Hyoun;
- Oh, Seul-Ki;
- Song, Wangyu;
- ... Lee, Seung-Beck;
- 외 1명
Citations
SCOPUS
0초록
We report on the fabrication and C-V characteristics of double layer NiSi2 nanocrystals (NCs) with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. The variation in threshold voltage shift ΔVTH) was measured for samples at different stress voltages. The ΔVTH increased with applied program voltage from 1.0 V at 3 V to 2.3 V at 7 V. Compared with SiO 2, ΔVTH is reduced to 0.2-0.4 V in each program voltages demonstrating possible multi-level-cell (MLC) operation.
키워드
Applied programs; C-V characteristic; Double layers; Multi-level; Nanofloating gate memory; Program voltage; Stress voltages; Threshold voltage shifts; Tunnel barrier; Nanocrystals; Nanoelectronics; Silicon compounds; Threshold voltage
- 제목
- Reduced distribution of threshold voltage shift in double layer NiSi 2 nanocrystals for nano-floating gate memory applications
- 저자
- Choi, Sung-Jin; Lee, Jun-Hyuk; Kim, Dong-Hyoun; Oh, Seul-Ki; Song, Wangyu; Choi, Seon-Jun; Lee, Seung-Beck
- 발행일
- 2010-03
- 유형
- Conference Paper
- 저널명
- INEC 2010 - 2010 3rd International Nanoelectronics Conference, Proceedings
- 페이지
- 1246 ~ 1247
- 언어
- ENG
- 출판사
- IEEE
- 발행국가
- 미국
- 분량
- 2 페이지
- ISSN
- P 0000-0000