An 8-GS/s 7-bit Eight-Way Time-Interleaved Partially Speculative Loop-Unrolled SAR ADC

초록

This paper presents an 8-GS/s, 7-bit, eight-way time-interleaved partially speculative loopunrolled (PSLU) successive approximation register (SAR) analog-to-digital converter (ADC). The proposed speculative method improves conversion speed by immediately converting two capacitive digital-to-analog converter (CDAC) outputs after the comparator's aperture window, reducing the conversion cycle to the sum of the aperture window, logic delay, and CDAC settling time. To improve efficiency, the speculative conversion is applied only to the upper-bit decisions, providing an optimal trade-off between speed and power consumption. In addition, a time-domain conversion (TDC) scheme resolves the least significant bit without requiring an extra conversion cycle, avoiding hardware overhead. To achieve the required bandwidth while ensuring high accuracy, the proposed PSLU SAR ADC is time-interleaved in a direct sampling architecture with a transmission-gate-based clock distribution circuit. Fabricated in a 28-nm CMOS process, the eightway time-interleaved 7-bit prototype achieves an 8-GS/s sampling rate, with a signal-to-noise-and-distortion ratio (SNDR) of 34.6 dB, a spurious-free dynamic range (SFDR) of 51 dB, and a power consumption is 19.7 mW. The Walden and Schreier figure-of-merit (FoMW and FoMS) are 56.1 fJ/conversion-step and 147.7 dB, respectively.

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