Demonstration of 3D-Extendible, Logic-Compatible Sub-1.8 v Asymmetric Double-Gate FeFETs with Sub-3.5 nm Ultrathin HZO for Analog CIM

초록

In this work, we demonstrate asymmetric doublegate (ADG) FeFETs utilizing sub-3.5 nm ultrathin HZO, achieving a wide memory window (MW) of 1.3 V at a logiccompatible operating voltage of 1.8 V. While aggressive ferroelectric thickness scaling is essential for reducing operating voltage, it typically suffers from severe polarization degradation and MW loss due to phase instability. We address this challenge by introducing a gate-coupling-ratio engineering approach within an ALD-based 3D-compatible process. The proposed ADG-FeFET exhibits a 3.4 × larger MW compared to conventional single-gate FeFETs and demonstrates superior reliability. Furthermore, the potential for analog compute-inmemory (CIM) is validated through stable multilevel operation with high linearity and system-level simulations. These results provide a practical pathway toward low-voltage, high-density FeFET technologies and next-generation analog CIM systems.

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