Tunneling field effect transistors (TFETs) with 3D fin-shaped channel structure and their electrical characteristics

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초록

In this study, we have demonstrated 3D fin-structured channel Silicon-On-Insulator (SOI) tunneling field effect transistor (TFET) to enhance transistor on-current (I-on) by reducing leakage current and enhancing gate controllability. By comparing with planar TFET, the subthreshold swing (S.S) value is apparently reduced by similar to 20 mV/dec with increased I-on using fin-typed TFET. Moreover, we have investigated impact of the interfacial layer (IL) modulation on the electrical characteristics of each planar TFET and fin-typed TFET, where IL modulation was performed by adopting modified chemical oxide as well as interface treatment. The IL modulation is substantial on the fin-typed TFET in terms of off leakage current (I-off) as well as threshold voltage instability (Delta V-th) against electrical stress, indicating 3D channel is more sensitive to interface condition. Our results suggest that alternative 3D structure with an appropriate interface treatment might be beneficial to attain better I-on while keeping lower S.S and I-off.

키워드

Tunneling field effect transistor (TFET)Fin-typed TFETInterfacial layer (IL)Subthreshold swing (S.S)Interface trap (N-it)Electric field effectsFinFETFins (heat exchange)IonsModulationSilicon on insulator technologyThreshold voltageTransistorsElectrical characteristicInterface conditionsInterface trap (NIT)Interfacial layerSilicon on insulator (SOI)Subthreshold swingThreshold-voltage instabilitiesTunneling field-effect transistorsTunnel field effect transistors
제목
Tunneling field effect transistors (TFETs) with 3D fin-shaped channel structure and their electrical characteristics
저자
Lim, DonghwanHan, HoonheeChoi, Changhwan
DOI
10.1016/j.sse.2019.01.003
발행일
2019-04
유형
Article
저널명
Solid-State Electronics
154
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