Effective Dipole Strength Modulation Using Imprinted Gadolinium Dipole (IGD) Layer to Achieve Fine Vt Tunability for Low Thermal Budget CFET Devices

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초록

We investigate dipole-first (DF) gate stacks using rare-earth oxides (REOs) to enable scalable multi-Vt options for advanced logic CFET devices. LaOx and GdOx DF stacks are systematically compared in terms of dipole strength, interface quality, trap charge density, and gate leakage. LaOx exhibits strong dipole behavior, resulting in a Vt reduction of ∼ 155 mV/cycle. GdOx shows a moderate dipole effect with a negative Vt shift of ∼ 80 mV/ cycle. However, the 1 cycledALD of GdOx induced an excessively strong dipole, leading to an abrupt Vt modulation. Based on this behavior, an imprinted Gd dipole (IGD) gate stack is designed to further modulate the effective dipole strength of a subsequent LaOx DF stack. The proposed IGD scheme achieves a fine Vt tunability of ∼ 40 mV/ cycle with negligible EOT penalty. In addition, the IGD stack reduces the effective trap density by 92% and suppresses gate leakage current by more than one order of magnitude compared to the conventional LaOx DF stack.

키워드

GadoliniumGadolinium compoundsLeakage currentsLogic gates
제목
Effective Dipole Strength Modulation Using Imprinted Gadolinium Dipole (IGD) Layer to Achieve Fine Vt Tunability for Low Thermal Budget CFET Devices
저자
Han, SangkukChoi, WonjaeChung, JaewonJang, HaesooPark, KyungwookLim, SangmyunPark, SoyoungJeong, SangwooKim, HanbyulPark, Yong JooAhn, JinhoChoi, Changhwan
DOI
10.1109/VLSITechnologyandCir65830.2026.11577561
발행일
2026-07
유형
Conference Paper
저널명
Digest of Technical Papers - Symposium on VLSI Technology
페이지
1 ~ 3