상세 보기
Bonding based channel transfer and low temperature process for monolithic 3D integration platform development
- Choi, R.;
- Yu, H.-Y.;
- Kim, H.;
- Ryu, H.-Y.;
- Bae, H.-K.;
- ... Choi, Chang hwan;
- 외 2명
Citations
SCOPUS
3초록
We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (< 450°C), low temperature (< 550°C) in-situ doped S/D selective SiGe epi process, low temperature (< 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.
키워드
Epitaxial Growth; Gate Stack; Laser Annealing; Low Temperature Bonding; Monolithic 3D; Bonding; Chemical bonds; Epitaxial growth; Integration; Ion implantation; Logic gates; Low temperature operations; Microelectronics; Monolithic integrated circuits; Silicon wafers; Three dimensional integrated circuits; Wafer bonding; 3-D integration; Channel transfer; Gate stacks; Laser annealing; Low power application; Low temperature bonding; Low temperatures; Low- temperature process; Temperature
- 제목
- Bonding based channel transfer and low temperature process for monolithic 3D integration platform development
- 저자
- Choi, R.; Yu, H.-Y.; Kim, H.; Ryu, H.-Y.; Bae, H.-K.; Choi, K.K.; Cha, Y.-W.; Choi, Chang hwan
- 발행일
- 2017-01
- 유형
- Conference Paper
- 저널명
- 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
- 언어
- ENG
- 출판사
- Institute of Electrical and Electronics Engineers Inc.
- ISSN
- P 0000-0000